The escalating demands for high density and performance associated with semiconductor devices, such as non-volatile, electrically erasable programmable read only memory (EEPROM) devices, require small design features, high reliability and increased manufacturing throughput. The reduction of design features, however, challenges the limitations of conventional methodology.
One particular problem with scaling memory devices to reduce their size is that the memory devices often exhibit degraded performance. For example, reducing the size of various structures in the memory devices, often results in an increased negative impact from fabrication processing techniques, such as etching techniques, deposition techniques, and the like. Techniques that perform well at larger sizes may introduce defects at a reduced scale. These problems may make it difficult for the memory device to be efficiently programmed and/or erased and, ultimately, may lead to device failure.